The invention will be described with particular reference to complementary MOS (CMOS) devices, although it is also applicable to either n-type or p-type MOS devices. CMOS devices are proving of great importance for high density integrated circuits because of their special properties, particularly their low current needs. For use in integrated circuits, it is important to minimize the surface area of the chip used by individual CMOS devices. To this end, CMOS devices with self-aligned silicided source/drain regions and with deposited oxide side-wall spacers to separate the channel edges from the source/drain regions have become important since they permit the convenient fabrication of high density arrays of such devices.
Standard silicided source/drain CMOS technology uses side-wall spacers which are formed by a process which basically involves firstly the selective anisotropic etching of a polycrystalline silicon layer to define gate regions with vertical side walls, next the conformal deposition of an oxide layer, and finally the selective anisotropic etching of the oxide layer. This results in a relatively complex process and process complexity usually results in reduced manufacturing yields.
The present invention is a simpler process which should result in increased process yields.